VR-Zone has posted an extensive article, discussing Intel's next-gen Haswell processor and the high-end 'Haswell-EP' platform in particular. This platform is designed for professional use, where multiple processors are placed on a single motherboard in either a server or workstation environment. Nevertheless, a consumer version of the platform will also be available, which is to be the successor to the current Sandy Bridge-E platform with its X79 chipset and socket LGA 2011. We'll discuss the features of this new Haswell-EP processor below.
The Haswell-EP will feature a double QPI-controller, required to communicate with other processors directly. The total available bandwidth will be twice as high, totaling 51.2 GB/s. A slower DMI interface controls the chipset communication.
The memory controller of the new Haswell-EP chips will have a quad-channel design, but will have two important changes. For one, the leaked slides show that Intel uses DDR4 memory. Furthermore, a so-called point-to-point connection is established between the memory modules and the processor, meaning only a single memory module is available per channel. In practice, this means that only four memory banks will be available per CPU socket. An increased storage capacity per module should prevent this from becoming a limiting factor. Current DDR3 modules are already available in modules of 8 GB, which in a quad-channel configuration would result in 32 GB per processor. DDR4 memory runs at up to 2133 MHz according to the specifications, although it is not unlikely that faster modules will be introduced in the future.
Double QPI interface and quad-channel DDR4 controller (Source: Chiphell)
The PCI-Express controller of the Haswell-EP has forty lanes, compliant to the PCI-Express 3.0 specifications. This means the platform is also suited for configurations with multiple graphics cards or rapid PCI-Express-based SSDs and raid controllers. The regular consumer Haswell processor will feature 24 PCI-Express 3.0 lanes.
Amount of cores
The transition to a 22nm process results in additional room for cores and cache memory. The slides VR-Zone posted mention 10+ cores, but with a total cache of up to 35 MB and a per-core cache amount of 2.5 MB, it can easily be observed that a fully-enabled Haswell-EP chip is likely to have fourteen cores. The L3-cache memory is shared across all cores, while each individual core has its own part of L2-cache. Like the Sandy Bridge and Ivy Bridge generation, the ring bus also returns for internal data transport.
Hyper-threading and Turbo
These features also return in the Haswell-EP processors, although the leaked slides show that Intel has improved its Turbo mode. The Haswell-EP is also capable of scaling its uncore frequency and adjusting its so-called P-state per core. These techniques should minimise the power consumption of the new chips.
The Haswell-EP CPU is likely to have a lot more cores, thanks to its smaller 22nm transistors (Source: Chiphell)
The Haswell-EP platform runs on the 'Wellsburg' chipset; a modern chip that is likely to feature 32nm transistors. The chipset will have its own clock generator, a USB 3.0 controller with six ports, ten SATA 6 Gbps connectors and 'enterprise' Rapid Storage Technology (RSTe). The chipset, which bears the model number C610, also provides support for SSD caching, several RAID levels and Gigabit ethernet. It's uncertain whether the latter will actually see be used as the faster 10 Gbit network technology and 'Infiniband' are quickly gaining ground in the business market. These controllers can be linked ot the PCI-Express interface. The chipset will have eight PCI-Express 2.0 lanes.
Despite the efficiency improvements, Intel's new high-end platform still requires quite some power, with TDP values ranging between 130 and 160 watts. With a TDP of 7 watts, the chipset is quite efficient.
The new C610 chipset will also be changed significantly (Source: Chiphell)